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oxidecomputer
quartz
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nathanaelhuffman running HDL simulations
simulation
#1078:
Commit
a234a41
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nathanaelhuffman
23s
metro-seq-2026-10-07-192253
metro-seq-2026-10-07-192253
23s
View workflow file
nathanaelhuffman Building FPGA bitstreams
fpga-build
#1092:
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a234a41
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nathanaelhuffman
28s
metro-seq-2026-10-07-192253
metro-seq-2026-10-07-192253
28s
View workflow file
nathanaelhuffman Building FPGA bitstreams
fpga-build
#1091:
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a234a41
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nathanaelhuffman
59m 46s
main
main
59m 46s
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nathanaelhuffman running HDL simulations
simulation
#1077:
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20m 54s
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20m 54s
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nathanaelhuffman running HDL simulations
simulation
#1076:
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nathanaelhuffman
27m 36s
ndh/fix-change-detector
ndh/fix-change-detector
27m 36s
View #540
View workflow file
nathanaelhuffman Building FPGA bitstreams
fpga-build
#1090:
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56m 0s
ndh/fix-change-detector
ndh/fix-change-detector
56m 0s
View #540
View workflow file
nathanaelhuffman Building FPGA bitstreams
fpga-build
#1089:
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0fae25e
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10s
ndh/fix-change-detector
ndh/fix-change-detector
10s
View #540
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nathanaelhuffman running HDL simulations
simulation
#1075:
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8s
ndh/fix-change-detector
ndh/fix-change-detector
8s
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nathanaelhuffman Building FPGA bitstreams
fpga-build
#1088:
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57m 28s
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57m 28s
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nathanaelhuffman running HDL simulations
simulation
#1074:
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22m 5s
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22m 5s
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nathanaelhuffman running HDL simulations
simulation
#1073:
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20m 45s
ndh/versal-sync-delay
ndh/versal-sync-delay
20m 45s
View #539
View workflow file
nathanaelhuffman Building FPGA bitstreams
fpga-build
#1087:
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25m 4s
ndh/versal-sync-delay
ndh/versal-sync-delay
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View #539
View workflow file
nathanaelhuffman running HDL simulations
simulation
#1072:
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20m 44s
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20m 44s
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nathanaelhuffman Building FPGA bitstreams
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#1086:
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27m 54s
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27m 54s
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nathanaelhuffman running HDL simulations
simulation
#1071:
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19m 30s
ndh/versal-sync-delay
ndh/versal-sync-delay
19m 30s
View workflow file
nathanaelhuffman Building FPGA bitstreams
fpga-build
#1085:
Commit
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3m 33s
ndh/versal-sync-delay
ndh/versal-sync-delay
3m 33s
View workflow file
nathanaelhuffman running HDL simulations
simulation
#1070:
Commit
f4610ab
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19m 27s
ndh/make-code-worse-for-vivado-bug
ndh/make-code-worse-for-vivado-bug
19m 27s
View #538
View workflow file
nathanaelhuffman Building FPGA bitstreams
fpga-build
#1084:
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3m 7s
ndh/make-code-worse-for-vivado-bug
ndh/make-code-worse-for-vivado-bug
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View #538
View workflow file
nathanaelhuffman Building FPGA bitstreams
fpga-build
#1083:
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2m 20s
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nathanaelhuffman running HDL simulations
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#1069:
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21m 4s
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main
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View workflow file
nathanaelhuffman Building FPGA bitstreams
fpga-build
#1082:
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16m 20s
ndh/versal-sync-delay
ndh/versal-sync-delay
16m 20s
View workflow file
nathanaelhuffman running HDL simulations
simulation
#1068:
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5m 28s
ndh/versal-sync-delay
ndh/versal-sync-delay
5m 28s
View workflow file
nathanaelhuffman Building FPGA bitstreams
fpga-build
#1081:
Commit
36a5c8e
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1m 26s
ndh/bins-too-for-ignitiion
ndh/bins-too-for-ignitiion
1m 26s
View #537
View workflow file
nathanaelhuffman running HDL simulations
simulation
#1067:
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36a5c8e
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33s
ndh/bins-too-for-ignitiion
ndh/bins-too-for-ignitiion
33s
View #537
View workflow file
nathanaelhuffman running HDL simulations
simulation
#1066:
Commit
7d6b54f
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23s
metro-ignition-2026-10-07-113937
metro-ignition-2026-10-07-113937
23s
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