hdl: use <view>'converse directly in ports rather than the package alias

hdl/ip/vhd/axi_blocks/axil8_resizer.vhd

@@ -13,7 +13,7 @@ use work.axil32x32_pkg;
 
 entity axil8_resizer is
       port(
-            fabric  : view axil32x32_pkg.axil_target;
+            fabric  : view axil32x32_pkg.axil_controller'converse;
             responder : view axil8x32_pkg.axil_controller
       );
 end entity;

hdl/ip/vhd/axi_blocks/axil_interconnect.vhd

@@ -27,7 +27,7 @@ entity axil_interconnect is
         reset : in std_logic;
 
         -- Responder I/F to the main initiator, which is a *target* interface
-        initiator : view axil26x32_pkg.axil_target;
+        initiator : view axil26x32_pkg.axil_controller'converse;
 
         -- Initiator I/Fs to the responder blocks, which is a *controller* interface
         responders : view (axil32x32_pkg.axil_controller) of axil32x32_pkg.axil_array_t(config_array'range)

hdl/ip/vhd/espi/espi_target_top.vhd

@@ -39,7 +39,7 @@ entity espi_target_top is
         clk_200m : in std_logic;
         reset_200m : in std_logic;
         -- Axilite interface
-        axi_if : view axil_target;
+        axi_if : view axil_controller'converse;
         -- phy interface
         cs_n  : in    std_logic;
         sclk  : in    std_logic;

hdl/ip/vhd/espi/link_layer/dbg_link_faker.vhd

@@ -31,11 +31,11 @@ entity dbg_link_faker is
         cs_n : out std_logic;
         alert_needed : in boolean;
         -- "Streaming" data recieved after deserialization
-        gen_resp       : view byte_sink;
+        gen_resp       : view byte_source'converse;
         -- "Streaming" data to serialize and transmit
         gen_cmd     : view byte_source;
 
-        dbg_chan : view dbg_periph_if;
+        dbg_chan : view dbg_regs_if'converse;
         dbg_espi_reset : out std_logic        
     );
 end entity;

hdl/ip/vhd/espi/link_layer/link_layer.vhd

@@ -32,7 +32,7 @@ entity link_layer is
         cmd_to_fifo: view byte_source;
 
         -- Response FIFO interface, data to host goes into this fifo
-        resp_from_fifo: view byte_sink;
+        resp_from_fifo: view byte_source'converse;
 
         -- System interface (from slow domain, already sync'd)
         wait_states : in std_logic_vector(3 downto 0);

hdl/ip/vhd/espi/peripheral_channel/uart_channel_top.vhd

@@ -32,7 +32,7 @@ entity uart_channel_top is
         stuff_wds : in std_logic_vector(15 downto 0);
 
         -- eSPI Transaction interface
-        host_to_sp_espi : view uart_data_sink;
+        host_to_sp_espi : view uart_data_source'converse;
         sp_to_host_espi : view uart_resp_src;
 
         -- Interfaces to the UART block

hdl/ip/vhd/espi/sys_regs/espi_regs.vhd

@@ -27,7 +27,7 @@ entity espi_regs is
         clk   : in    std_logic;
         reset : in    std_logic;
         -- axi interface
-        axi_if : view axil_target;
+        axi_if : view axil_controller'converse;
         post_code      : in std_logic_vector(31 downto 0);
         post_code_valid : in std_logic;
         espi_reset : in std_logic;
@@ -36,7 +36,7 @@ entity espi_regs is
         stuff_fifo : out std_logic;
         stuff_wds : out std_logic_vector(15 downto 0);
         -- read-only view of eSPI spec registers
-        spec_regs_view : view spec_regs_sink;
+        spec_regs_view : view spec_regs_source'converse;
         -- debug interface
         dbg_chan : view dbg_regs_if;
         to_host_tx_fifo_usedwds : in std_logic_vector(12 downto 0);

hdl/ip/vhd/espi/txn_layer/command_processor.vhd

@@ -26,8 +26,8 @@ entity command_processor is
         -- register layer connections
         running_crc    : in    std_logic_vector(7 downto 0);
         clear_rx_crc   : out   std_logic;
-        regs_if        : view bus_side;
-        vwire_if       : view vwire_cmd_side;
+        regs_if        : view regs_side'converse;
+        vwire_if       : view vwire_regs_side'converse;
         command_header : out   espi_cmd_header;
         response_done  : in    boolean;
         post_code      : out std_logic_vector(31 downto 0);
@@ -38,15 +38,15 @@ entity command_processor is
         -- the host gets an unsuccessful completion for them.
         flash_writes_allowed : in std_logic;
         -- flash channel requests
-        flash_req : view flash_chan_req_source;
+        flash_req : view flash_chan_req_sink'converse;
         -- uart channel put interface here
         host_to_sp_espi : view uart_data_source;
 
         -- Link-layer connections
         is_rx_crc_byte     : out   boolean;
         chip_sel_active : in    std_logic;
         -- "Streaming" data to serialize and transmit
-        data_from_host : view byte_sink
+        data_from_host : view byte_source'converse
     );
 end entity;
 

hdl/ip/vhd/espi/txn_layer/link_to_txn_bridge.vhd

@@ -32,20 +32,20 @@ entity link_to_txn_bridge is
 
         -- To/From the qspi link layer
         -- Fast clock domain
-        qspi_cmd : view byte_sink;
+        qspi_cmd : view byte_source'converse;
         qspi_resp : view byte_source;
         qspi_cs_n : in std_logic;
 
         -- To/From the transaction generation layer
         -- Slow clock domain
-        gen_cmd : view byte_sink;
+        gen_cmd : view byte_source'converse;
         gen_resp : view byte_source;
         gen_cs_n : in std_logic;
 
         -- To/From the transaction layer
         -- Slow clock domain
         txn_cmd : view byte_source;
-        txn_resp : view byte_sink;
+        txn_resp : view byte_source'converse;
         txn_csn : out std_logic;
     );
 end entity;

hdl/ip/vhd/espi/txn_layer/response_processor.vhd

@@ -31,9 +31,9 @@ entity response_processor is
         is_tx_last_byte : out   boolean;
 
         -- flash channel responses
-        flash_resp : view flash_chan_resp_sink;
+        flash_resp : view flash_chan_resp_source'converse;
         -- uart channel responses
-        sp_to_host_espi : view uart_resp_sink;
+        sp_to_host_espi : view uart_resp_src'converse;
 
         alert_needed : out   boolean;
         -- Packed status_t that was last sent on the wire

hdl/ip/vhd/espi/txn_layer/txn_layer_top.vhd

@@ -21,21 +21,21 @@ entity txn_layer_top is
         reset : in    std_logic;
 
         -- register layer connections
-        regs_if : view    bus_side;
+        regs_if : view    regs_side'converse;
         post_code      : out std_logic_vector(31 downto 0);
         post_code_valid : out std_logic;
         -- vwire channel connections
-        vwire_if : view vwire_cmd_side;
+        vwire_if : view vwire_regs_side'converse;
         -- flash channel status
         flash_np_free : in    std_logic;
         flash_c_avail : in    std_logic;
         -- flash channel requests/responses
         flash_writes_allowed : in std_logic;
-        flash_req  : view flash_chan_req_source;
-        flash_resp : view flash_chan_resp_sink;
+        flash_req  : view flash_chan_req_sink'converse;
+        flash_resp : view flash_chan_resp_source'converse;
         -- uart channel requests/responses
         host_to_sp_espi : view uart_data_source;
-        sp_to_host_espi : view uart_resp_sink;
+        sp_to_host_espi : view uart_resp_src'converse;
         -- uart channel status
         pc_free : in std_logic;
         pc_avail : in std_logic;
@@ -55,7 +55,7 @@ entity txn_layer_top is
         response_done   : out   boolean;
         aborted_due_to_bad_crc : out boolean;
         -- "Streaming" data to serialize and transmit
-        data_from_host : view byte_sink;
+        data_from_host : view byte_source'converse;
         live_espi_status : out std_logic_vector(15 downto 0);
         -- Packed status_t that was last sent on the wire
         last_resp_status : out std_logic_vector(15 downto 0)

hdl/ip/vhd/hash_engine/hash_engine_regs.vhd

@@ -19,7 +19,7 @@ entity hash_engine_regs is
         reset : in    std_logic;
 
         -- axi interface
-        axi_if : view axil_target;
+        axi_if : view axil_controller'converse;
 
         -- Control strobes. CONTROL.start and CONTROL.abort are self clearing, so
         -- they leave here as single cycle pulses rather than as a register.

hdl/ip/vhd/hash_engine/hash_engine_top.vhd

@@ -52,7 +52,7 @@ entity hash_engine_top is
         reset : in    std_logic;
 
         -- Axilite interface
-        axi_if : view axil_target;
+        axi_if : view axil_controller'converse;
 
         -- Hardware request, see above. Leave hw_req unconnected on a design
         -- without a requester.

hdl/ip/vhd/i2c/controller/regs/i2c_ctrl_regs.vhd

@@ -17,7 +17,7 @@ entity i2c_ctrl_regs is
     port (
         clk     : in    std_logic;
         reset   : in    std_logic;
-        axi_if  : view  axil_target;
+        axi_if  : view  axil_controller'converse;
     );
 end entity;
 

hdl/ip/vhd/i2c/controller/txn_layer/i2c_ctrl_txn_layer.vhd

@@ -42,7 +42,7 @@ entity i2c_ctrl_txn_layer is
         txn_status : out txn_status_t;
 
         -- Transmit data stream
-        tx_st_if    : view axi_st8_pkg.axi_st_sink;
+        tx_st_if    : view axi_st8_pkg.axi_st_source'converse;
 
         -- Received data stream
         rx_st_if    : view axi_st8_pkg.axi_st_source;

hdl/ip/vhd/info/info.vhd

@@ -21,7 +21,7 @@ entity info is
         hubris_compat_pins: in std_logic_vector(hubris_compat_num_bits-1 downto 0);
         -- axi interface. This is not using VHDL2019 views so that it's compatible with
         -- GHDL/yosys based toolchains
-        axi_if : view axil_target;
+        axi_if : view axil_controller'converse;
 
 
     );

hdl/ip/vhd/sha3/sha3_256.vhd

@@ -62,7 +62,7 @@ entity sha3_256 is
         -- AXI streaming has no zero-beat packet, so the empty message is not
         -- representable here; a consumer needing SHA3-256("") should use the
         -- known constant.
-        msg_if : view axi_st8_pkg.axi_st_pkt_sink;
+        msg_if : view axi_st8_pkg.axi_st_pkt_source'converse;
 
         -- digest(7 downto 0) is hash byte 0, ie the leftmost byte of the
         -- conventional hex string. Held stable until init or the next message

hdl/ip/vhd/spi_nor_controller/spi_nor_regs.vhd

@@ -14,7 +14,7 @@ entity spi_nor_regs is
         clk   : in    std_logic;
         reset : in    std_logic;
         -- axi interface
-        axi_if : view axil_target;
+        axi_if : view axil_controller'converse;
 
         -- system interface
         addr             : out   addr_type;

hdl/ip/vhd/spi_nor_controller/spi_nor_top.vhd

@@ -27,7 +27,7 @@ entity spi_nor_top is
         clk   : in    std_logic;
         reset : in    std_logic;
         -- Axilite interface
-        axi_if : view axil_target;
+        axi_if : view axil_controller'converse;
         -- qspi interface
         cs_n  : out   std_logic;
         sclk  : out   std_logic;

hdl/projects/cosmo_seq/board_support/board_support_top.vhd

@@ -31,7 +31,7 @@ entity board_support is
         fpga1_status_led : out std_logic;
         hubris_compat_ver : in std_logic_vector(2 downto 0);
         -- AXI interface for the "info" block
-        info_axi_if : view axil_target;
+        info_axi_if : view axil_controller'converse;
         is_rev1 : out std_logic;  -- tied high if rev1 board
         is_rev2 : out std_logic  -- tied high if rev2 board
     );

hdl/projects/cosmo_seq/debug_module/debug_header.vhd

@@ -53,7 +53,7 @@ entity debug_header is
         mux2_sel_pins : in std_logic_vector(1 downto 0); -- mux2 sel pins debug output to pins
         mux3_sel_pins : in std_logic_vector(1 downto 0); -- mux3 sel pins debug output to pins
         -- T6 signals
-        nic_dbg_pins : view nic_debug_dbg;
+        nic_dbg_pins : view nic_debug_seq_ss'converse;
         -- sp5 toggle pins
         sp5_debug2_pin : in std_logic;
 

hdl/projects/cosmo_seq/debug_module/debug_module_top.vhd

@@ -22,7 +22,7 @@ entity debug_module_top is
         clk : in std_logic;
         reset : in std_logic;
 
-        axi_if : view axil_target;
+        axi_if : view axil_controller'converse;
 
         in_a0 : in std_logic;
         sp5_debug2_pin : in std_logic;
@@ -31,7 +31,7 @@ entity debug_module_top is
         fpga2_hp_irq_n : in std_logic;
         hp_int_n : in std_logic;
 
-        uart_dbg_if : view uart_dbg_dbg_if;
+        uart_dbg_if : view uart_dbg_ss_if'converse;
 
         -- hotplug
         i2c_sp5_to_fpgax_hp_sda: in std_logic;
@@ -67,7 +67,7 @@ entity debug_module_top is
         espi0_sp5_to_fpga1_dat: in std_logic_vector(3 downto 0);
         espi_resp_csn: in std_logic;
         --T6 signals
-        nic_dbg_pins : view nic_debug_dbg;
+        nic_dbg_pins : view nic_debug_seq_ss'converse;
 
         fpga1_spare_v1p8 : out std_logic_vector(7 downto 0); -- 8 spare pins on the debug header
 

hdl/projects/cosmo_seq/dimms_subsystem/dimms_subsystem_top.vhd

@@ -24,7 +24,7 @@ entity dimms_subsystem_top is
         reset       : in std_logic;
 
         -- AXI-Lite interface
-        axi_if : view axil8x32_pkg.axil_target;
+        axi_if : view axil8x32_pkg.axil_controller'converse;
 
         in_a0 : in std_logic;
 

hdl/projects/cosmo_seq/dimms_subsystem/proxy_channel/spd_cache.vhd

@@ -21,7 +21,7 @@ entity spd_cache is
         raddr       : in std_logic_vector(7 downto 0);
         rdata       : out std_logic_vector(31 downto 0);
         -- streaming bus from i2c controller
-        i2c_rx_st_if        : view axi_st8_pkg.axi_st_sink
+        i2c_rx_st_if        : view axi_st8_pkg.axi_st_source'converse
 
     );
 end entity;

hdl/projects/cosmo_seq/dimms_subsystem/regs/spd_regs.vhd

@@ -20,13 +20,13 @@ entity spd_regs is
         clk : in std_logic;
         reset : in std_logic;
         -- AXI-Lite interface
-        axi_if : view axil8x32_pkg.axil_target;
+        axi_if : view axil8x32_pkg.axil_controller'converse;
 
         dimm_pcamp : in dimm_pcamp_type;
 
         -- FPGA I2C Interface
-        bus0 : view reg_side;
-        bus1 : view reg_side
+        bus0 : view channel_side'converse;
+        bus1 : view channel_side'converse
     );
 end entity;
 

hdl/projects/cosmo_seq/dimms_subsystem/regs/txn_buffer.vhd

@@ -17,7 +17,7 @@ entity txn_buffer is
 
         regs_if : view regs_buf_buf_side;
 
-        i2c_rx_st_if        : view axi_st8_pkg.axi_st_sink;
+        i2c_rx_st_if        : view axi_st8_pkg.axi_st_source'converse;
         i2c_tx_st_if        : view axi_st8_pkg.axi_st_source;
     );
 end entity;

hdl/projects/cosmo_seq/sequencer/seq_sync.vhd

@@ -29,13 +29,13 @@ entity seq_sync is
         -- internal, synchronized interfaces
         rail_masks : in rails_type;
         sp5_seq_test_mask : in sp5_seq_test_mask_type;
-        early_power : view early_power_on_board;
-        ddr_bulk: view ddr_bulk_at_reg;
-        group_a : view group_a_power_at_reg;
-        group_b : view group_b_power_at_reg;
-        group_c : view group_c_power_at_reg;
-        sp5_seq : view sp5_seq_at_sp5;
-        reg_alert_l : view power_alert_at_reg;
+        early_power : view early_power_at_fpga'converse;
+        ddr_bulk: view ddr_bulk_power_at_fpga'converse;
+        group_a : view group_a_power_at_fpga'converse;
+        group_b : view group_b_power_at_fpga'converse;
+        group_c : view group_c_power_at_fpga'converse;
+        sp5_seq : view sp5_seq_at_fpga'converse;
+        reg_alert_l : view power_alert_at_fpga'converse;
     );
     end entity;
 

hdl/projects/cosmo_seq/sequencer/sequencer_regs.vhd

@@ -21,7 +21,7 @@ entity sequencer_regs is
 
         irq_l_out : out std_logic;
         allow_backplane_pcie_clk : out std_logic;
-        axi_if : view axil8x32_pkg.axil_target;
+        axi_if : view axil8x32_pkg.axil_controller'converse;
         -- from early block
         early_power_ctrl: out early_power_ctrl_type;
         early_power_rdbks : in early_power_rdbks_type;

hdl/projects/cosmo_seq/sequencer/sp5_sequencer.vhd

@@ -34,7 +34,7 @@ entity sp5_sequencer is
         clk : in std_logic;
         reset : in std_logic;
 
-        axi_if : view axil8x32_pkg.axil_target;
+        axi_if : view axil8x32_pkg.axil_controller'converse;
         irq_l_out : out std_logic;
         -- These signals are useful throughout the design for dealing with
         -- buffers, a0-domain "reset" kinds of things etc

hdl/projects/cosmo_seq/sequencer/t6_sync.vhd

@@ -22,8 +22,8 @@ entity t6_sync is
         nic_rails_pins : view nic_power_at_fpga;
         nic_seq_pins: view nic_seq_at_fpga;
         -- internal, synchronized interfaces
-        nic_rails : view nic_power_at_reg;
-        nic_seq: view nic_seq_at_nic
+        nic_rails : view nic_power_at_fpga'converse;
+        nic_seq: view nic_seq_at_fpga'converse
     );
 end entity;