Ndh/metro ignition

.github/filters.yml

@@ -37,4 +37,7 @@ metro_seq:
   - 'hdl/projects/cosmo_seq/**/*'
 
 cosmo_ignition:
-  - 'hdl/projects/cosmo_ignition/**/*'
+  - 'hdl/projects/cosmo_ignition/**/*'
+
+metro_ignition:
+  - 'hdl/projects/metro_ignition/**/*'

hdl/projects/cosmo_ignition/BUCK

@@ -8,6 +8,7 @@ vhdl_unit(
     deps = [
         "//hdl/ip/vhd/ignition/target:ignition_target_common",
         "//hdl/ip/vhd/ignition/target:ignition_io",
+        "//hdl/ip/vhd/synchronizers:meta_sync",
     ],
     standard = "2008",
 )

hdl/projects/cosmo_ignition/cosmo_ignition_top.vhd

@@ -57,7 +57,19 @@ architecture rtl of cosmo_ignition_top is
     signal led_counter : unsigned(24 downto 0) := (others => '0');
     signal reset_sync1 : std_logic;
     signal reset_syncd : std_logic;
-
+    signal a2_pg_syncd_combined: std_logic;
+    signal v3p3_fpga2_a2_pg_syncd : std_logic;
+    signal v1p2_fpga2_a2_pg_syncd : std_logic;
+    signal v2p5_fpga2_a2_pg_syncd : std_logic;
+    signal v5p0_sys_a2_pg_syncd : std_logic;
+    signal v3p3_sys_a2_pg_syncd : std_logic;
+    signal v1p8_sys_a2_pg_syncd : std_logic;
+    signal v1p0_mgmt_a2_pg_syncd : std_logic;
+    signal v2p5_mgmt_a2_pg_syncd : std_logic;
+    signal v12_sys_a2_pg_l_syncd : std_logic;
+    signal main_hsc_pg_syncd : std_logic;
+    signal a3_pwr_fault_l : std_logic;
+
 begin
     rst_sync: process(clk_50mhz_ign_trgt_fpga, ign_trgt_fpga_design_reset_l)
     begin
@@ -71,6 +83,44 @@ begin
         end if;
     end process;
 
+    -- Deal with a big batch of input PGs.
+    pg_sync_inst: entity work.pg_sync
+     port map(
+        clk => clk_50mhz_ign_trgt_fpga,
+        v3p3_fpga2_a2_pg => v3p3_fpga2_a2_pg,
+        v1p2_fpga2_a2_pg => v1p2_fpga2_a2_pg,
+        v2p5_fpga2_a2_pg => v2p5_fpga2_a2_pg,
+        v5p0_sys_a2_pg => v5p0_sys_a2_pg,
+        v3p3_sys_a2_pg => v3p3_sys_a2_pg,
+        v1p8_sys_a2_pg => v1p8_sys_a2_pg,
+        v1p0_mgmt_a2_pg => v1p0_mgmt_a2_pg,
+        v2p5_mgmt_a2_pg => v2p5_mgmt_a2_pg,
+        v12_sys_a2_pg_l => v12_sys_a2_pg_l,
+        main_hsc_pg => main_hsc_pg,
+        v3p3_fpga2_a2_pg_syncd => v3p3_fpga2_a2_pg_syncd,
+        v1p2_fpga2_a2_pg_syncd => v1p2_fpga2_a2_pg_syncd,
+        v2p5_fpga2_a2_pg_syncd => v2p5_fpga2_a2_pg_syncd,
+        v5p0_sys_a2_pg_syncd => v5p0_sys_a2_pg_syncd,
+        v3p3_sys_a2_pg_syncd => v3p3_sys_a2_pg_syncd,
+        v1p8_sys_a2_pg_syncd => v1p8_sys_a2_pg_syncd,
+        v1p0_mgmt_a2_pg_syncd => v1p0_mgmt_a2_pg_syncd,
+        v2p5_mgmt_a2_pg_syncd => v2p5_mgmt_a2_pg_syncd,
+        v12_sys_a2_pg_l_syncd => v12_sys_a2_pg_l_syncd,
+        main_hsc_pg_syncd => main_hsc_pg_syncd
+    );
+
+    -- combine these to pass on as a single A2 power-good signal
+    a2_pg_syncd_combined <= v3p3_fpga2_a2_pg_syncd and
+                             v1p2_fpga2_a2_pg_syncd and
+                             v2p5_fpga2_a2_pg_syncd and
+                             v5p0_sys_a2_pg_syncd and
+                             v3p3_sys_a2_pg_syncd and
+                             v1p8_sys_a2_pg_syncd and
+                             v1p0_mgmt_a2_pg_syncd and
+                             v2p5_mgmt_a2_pg_syncd and
+                             v12_sys_a2_pg_l_syncd;
+
+    a3_pwr_fault_l <= '0' when main_hsc_pg_syncd = '1' else '1';
      -- Blink an LED at some rate
     led: process(clk_50mhz_ign_trgt_fpga, reset_syncd)
     begin
@@ -98,8 +148,8 @@ begin
         ignit_to_ibc_pwren => ibc_en,
         hotswap_restart_l => hotswap_restart_l,
         ignit_led_l => ign_trgt_fpga_debug_led,
-        a3_pwr_fault_l => '1',
-        a2_pg => '1',
+        a3_pwr_fault_l => a3_pwr_fault_l,
+        a2_pg => a2_pg_syncd_combined,
         sp_fault_l => sp_fault_l,
         rot_fault_l => rot_fault_l,
         push_btn_l => '1',

hdl/projects/cosmo_ignition/pg_sync.vhd

@@ -0,0 +1,82 @@
+-- This Source Code Form is subject to the terms of the Mozilla Public
+-- License, v. 2.0. If a copy of the MPL was not distributed with this
+-- file, You can obtain one at https://mozilla.org/MPL/2.0/.
+
+-- The power-good inputs come straight from regulators and the hot-swap
+-- controller, so they are asynchronous to the system clock and need to be
+-- synchronized before any logic consumes them.
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity pg_sync is
+    port (
+        clk : in std_logic;
+
+        v3p3_fpga2_a2_pg : in std_logic;
+        v1p2_fpga2_a2_pg : in std_logic;
+        v2p5_fpga2_a2_pg : in std_logic;
+        v5p0_sys_a2_pg : in std_logic;
+        v3p3_sys_a2_pg : in std_logic;
+        v1p8_sys_a2_pg : in std_logic;
+        v1p0_mgmt_a2_pg : in std_logic;
+        v2p5_mgmt_a2_pg : in std_logic;
+        v12_sys_a2_pg_l : in std_logic;
+        main_hsc_pg : in std_logic;
+
+        v3p3_fpga2_a2_pg_syncd : out std_logic;
+        v1p2_fpga2_a2_pg_syncd : out std_logic;
+        v2p5_fpga2_a2_pg_syncd : out std_logic;
+        v5p0_sys_a2_pg_syncd : out std_logic;
+        v3p3_sys_a2_pg_syncd : out std_logic;
+        v1p8_sys_a2_pg_syncd : out std_logic;
+        v1p0_mgmt_a2_pg_syncd : out std_logic;
+        v2p5_mgmt_a2_pg_syncd : out std_logic;
+        v12_sys_a2_pg_l_syncd : out std_logic;
+        main_hsc_pg_syncd : out std_logic
+    );
+end entity;
+
+architecture rtl of pg_sync is
+    constant NUM_PGS : integer := 10;
+    signal async_pgs : std_logic_vector(NUM_PGS - 1 downto 0);
+    signal syncd_pgs : std_logic_vector(NUM_PGS - 1 downto 0);
+begin
+
+    async_pgs <= (
+        9 => v3p3_fpga2_a2_pg,
+        8 => v1p2_fpga2_a2_pg,
+        7 => v2p5_fpga2_a2_pg,
+        6 => v5p0_sys_a2_pg,
+        5 => v3p3_sys_a2_pg,
+        4 => v1p8_sys_a2_pg,
+        3 => v1p0_mgmt_a2_pg,
+        2 => v2p5_mgmt_a2_pg,
+        1 => v12_sys_a2_pg_l,
+        0 => main_hsc_pg
+    );
+
+    sync_gen: for i in async_pgs'range generate
+        meta_sync_inst: entity work.meta_sync
+         generic map(
+            stages => 2
+        )
+         port map(
+            async_input => async_pgs(i),
+            clk => clk,
+            sycnd_output => syncd_pgs(i)
+        );
+    end generate;
+
+    v3p3_fpga2_a2_pg_syncd <= syncd_pgs(9);
+    v1p2_fpga2_a2_pg_syncd <= syncd_pgs(8);
+    v2p5_fpga2_a2_pg_syncd <= syncd_pgs(7);
+    v5p0_sys_a2_pg_syncd <= syncd_pgs(6);
+    v3p3_sys_a2_pg_syncd <= syncd_pgs(5);
+    v1p8_sys_a2_pg_syncd <= syncd_pgs(4);
+    v1p0_mgmt_a2_pg_syncd <= syncd_pgs(3);
+    v2p5_mgmt_a2_pg_syncd <= syncd_pgs(2);
+    v12_sys_a2_pg_l_syncd <= syncd_pgs(1);
+    main_hsc_pg_syncd <= syncd_pgs(0);
+
+end rtl;

hdl/projects/metro_ignition/BUCK

@@ -0,0 +1,22 @@
+load("//tools:hdl.bzl", "vhdl_unit")
+load("//tools:yosys.bzl", "ice40_bitstream")
+
+vhdl_unit(
+    name = "metro_ignition_top",
+    srcs = glob(["*.vhd"]),
+    deps = [
+        "//hdl/ip/vhd/ignition/target:ignition_target_common",
+        "//hdl/ip/vhd/ignition/target:ignition_io",
+        "//hdl/ip/vhd/synchronizers:meta_sync",
+    ],
+    standard = "2008",
+)
+
+ice40_bitstream(
+    name = "metro_ignition",
+    top_entity_name = "metro_ignition_top",
+    top = ":metro_ignition_top",
+    family = "hx8k",
+    package = "bg121",
+    pinmap = "metro_ignition.pcf",
+)

hdl/projects/metro_ignition/metro_ignition.pcf

@@ -0,0 +1,50 @@
+set_io --warn-no-port ign_trgt_fpga_debug_led[0] A11
+set_io --warn-no-port ign_trgt_fpga_debug_led[1] A10
+set_io --warn-no-port ign_trgt_fpga_debug_led[2] C9
+set_io --warn-no-port ign_trgt_fpga_debug_led[3] B9
+set_io --warn-no-port ign_trgt_fpga_spare_v3p3[0] B8
+set_io --warn-no-port ign_trgt_fpga_spare_v3p3[1] A9
+set_io --warn-no-port ign_trgt_fpga_spare_v3p3[2] C8
+set_io --warn-no-port ign_trgt_fpga_spare_v3p3[3] D7
+set_io --warn-no-port ign_trgt_fpga_spare_v3p3[4] A8
+set_io --warn-no-port ign_trgt_fpga_spare_v3p3[5] C7
+set_io --warn-no-port ign_trgt_fpga_spare_v3p3[6] A7
+set_io --warn-no-port ign_trgt_fpga_spare_v3p3[7] B7
+set_io --warn-no-port clk_50mhz_ign_trgt_fpga B6
+set_io --warn-no-port ign_trgt_id[0] A5
+set_io --warn-no-port ign_trgt_id[1] B5
+set_io --warn-no-port ign_trgt_id[2] A4
+set_io --warn-no-port ign_trgt_id[3] B4
+set_io --warn-no-port ign_trgt_id[4] A3
+set_io --warn-no-port ign_trgt_id[5] B3
+set_io --warn-no-port ign_trgt_id[6] A2
+set_io --warn-no-port ign_trgt_id[7] A1
+set_io --warn-no-port ign_trgt_fpga_lvds_status_led_en_l L1
+set_io --warn-no-port ign_trgt_fpga_pushbutton_reset_l L5
+set_io --warn-no-port ign_trgt_fpga_design_reset_l K6
+set_io --warn-no-port lvds_rsw0_to_ign_trgt_fpga_p B2
+#set_io --warn-no-port lvds_rsw0_to_ign_trgt_fpga_n B1
+# Note: p/n un-swapped in FPGA
+set_io --warn-no-port lvds_ign_trgt_fpga_to_rsw0_p C2
+set_io --warn-no-port lvds_ign_trgt_fpga_to_rsw0_n C1
+set_io --warn-no-port lvds_rsw1_to_ign_trgt_fpga_p G2
+#set_io --warn-no-port lvds_rsw1_to_ign_trgt_fpga_n G1
+# Note: p/n un-swapped in FPGA
+set_io --warn-no-port lvds_ign_trgt_fpga_to_rsw1_p H2
+set_io --warn-no-port lvds_ign_trgt_fpga_to_rsw1_n H1
+set_io --warn-no-port v3p3_fpga2_a2_pg J11
+set_io --warn-no-port v1p2_fpga2_a2_pg K11
+set_io --warn-no-port v2p5_fpga2_a2_pg H10
+set_io --warn-no-port main_hsc_restart G10
+set_io --warn-no-port ibc_en G11
+set_io --warn-no-port v5p0_sys_a2_pg F11
+set_io --warn-no-port v3p3_sys_a2_pg E10
+set_io --warn-no-port v1p8_sys_a2_pg E9
+set_io --warn-no-port v1p0_mgmt_a2_pg D9
+set_io --warn-no-port v2p5_mgmt_a2_pg E11
+set_io --warn-no-port v12_sys_a2_pg_l D11
+set_io --warn-no-port main_hsc_pg D10
+set_io --warn-no-port sp_fault_l C11
+set_io --warn-no-port rot_fault_l B11
+
+set_frequency clk_50mhz_ign_trgt_fpga 50