`core::num::f16b` Rust's 16bit Brain Float by Jamesbarford · Pull Request #160859 · rust-lang/rust

Jamesbarford · 2026-08-10T14:27:46Z

Implements the RFC: f16b type. Best reviewed commit by commit, happy to split into separate PRs if that is deemed easier to review. However the line count and surface area is, in my opinion, reasonably small.

Adds;

ABI plumbing for the f16b along with bfloat lang item to work with LLVM, GCC is explicitly unimplemented!(...)
f16b feature gate, page for f16b on libruscdoc and a struct bf16 in core::num
Tests
Treat f16b as a scalar primitive for scalable vectors

Issues;

rustbot · 2026-08-10T14:27:50Z

Some changes occurred in compiler/rustc_attr_ir

cc @jdonszelmann, @JonathanBrouwer

This PR changes rustc_public

cc @oli-obk, @celinval, @ouz-a, @makai410

rustc_codegen_gcc is developed in its own repository. If possible, consider making this change to rust-lang/rustc_codegen_gcc instead.

cc @antoyo, @GuillaumeGomez

rustbot · 2026-08-10T14:27:54Z

r? @jieyouxu

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jieyouxu · 2026-08-10T14:45:34Z

@rustbot reroll

antoyo · 2026-08-10T14:48:39Z

    }

+    fn type_f16b(&self) -> Type<'gcc> {
+        bug!("f16b is not supported by the GCC codegen backend")


I believe GCC actually supports this type: https://github.com/rust-lang/gccjit.rs/blob/master/src/context.rs#L1482

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Thanks 😄, I will aim to add it in a follow up PR 👍

Actually, as @folkertdev pointed out, it was a doddle. So I've included the implementation in the PR 👍

rustbot · 2026-08-10T14:48:49Z

rustc_codegen_cranelift is developed in its own repository. If possible, consider making this change to rust-lang/rustc_codegen_cranelift instead.

cc @bjorn3

rustbot · 2026-08-12T12:03:56Z

Some changes occurred in cfg and check-cfg configuration

cc @Urgau

miri is developed in its own repository. If the Miri part of this change can be broken out, consider making this change to rust-lang/miri instead. However, if Miri needs adjusting for rustc changes, just ignore this message.

cc @rust-lang/miri

mati865 · 2026-08-12T13:36:14Z

I'm not a good reviewer for this change. Can somebody here pick it up rather than blindly rerolling?

folkertdev · 2026-08-12T13:54:02Z

r? me

@folkertdev

…lkertdev Make sin, cos, exp, exp2, log, log2, log10 generic Rebased and smaller version of rust-lang/rust#153934 Following `fabs`, make the `sin`, `cos`, `exp`, `exp2`, `log`, `log2` and `log10` intrinsics generic over the float type, rather than having four variants per float type. The first two commits are purely stylistic: - reorganised Cranelift code to make following changes simpler - moved a misplaced comment in `compiler/rustc_codegen_llvm/src/intrinsic.rs` that caused `x fmt` to give up The last commit actually makes them generic! Most code is a bit simpler, ~~and this will also hopefully simplify adding support for these intrinsics for the future [`bf16` type](rust-lang/rust#160859 :) Unfortunately both GCC and Cranelift backend changes are a bit churny. Their code is a bit, opaque, to put it kindly, and I didn't want to refactor those here. r? @folkertdev cc @RalfJung

Jamesbarford · 2026-09-15T08:13:08Z

@bors try jobs=test-various,aarch64-apple-,-gnu-nopt-,x86_64-mingw-,aarch64-msvc-*,arm-android

`core::num::f16b` Rust's 16bit Brain Float try-job: test-various try-job: aarch64-apple-* try-job: *-gnu-nopt-* try-job: x86_64-mingw-* try-job: aarch64-msvc-* try-job: arm-android

rust-bors · 2026-09-15T08:14:07Z

💔 Test for 8f68b95 failed: CI. Failed job:

Calculate job matrix (web logs, enhanced plaintext logs)

Jamesbarford · 2026-09-15T10:22:13Z

I believe some of the jobs were renamed

@bors try jobs=test-various,test-aarch64-apple-,-gnu-nopt-,test-x86_64-mingw-,test-aarch64-msvc-*,test-arm-android

`core::num::f16b` Rust's 16bit Brain Float try-job: test-various try-job: test-aarch64-apple-* try-job: *-gnu-nopt-* try-job: test-x86_64-mingw-* try-job: test-aarch64-msvc-* try-job: test-arm-android

rust-bors · 2026-09-15T13:16:05Z

☀️ Try build successful (CI)
Build commit: 2027cd7 (2027cd7f37bc10f8ed9010e7e13772d9306d7d42)
Base parent: c26ce70 (c26ce708de5d14682647895d2f3caf38f70b5aa6)

folkertdev

Some final nits, but otherwise I think this looks good

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tgross35

Few small requests but overall LGTM

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tgross35 · 2026-09-15T21:12:18Z

+// RISCV64: fmv.x.w a0, fa0
+// RISCV64-NEXT: lui a1, 1048560
+// RISCV64-NEXT: or a0, a0, a1
+// RISCV64-NEXT: fmv.w.x fa0, a0
+// RISCV64-NEXT: ret


It seems to be setting the high bits to 0xffff here, which is kind of weird. I assume the ABI permits garbage in the upper bits (looking at what it does for f16b_to_bits) rather than requiring 0xffff.... for returns but apparently not passing? Seems worth an LLVM optimization issue if there isn't one.

Cc @beetrees I'm sure you have a better idea about this.

RISC-V uses NaN-boxing for its floating point registers (which f16b is passed/returned in on all hard-float ABIs), so the high bits must be set to all 1s. Without the zfhmin/zfbfmin extensions, the 32-bit move instructions have to be used, meaning the bits have to set to 1 manually. LLVM currently doesn't seem to keep track of whether the high bits have been set or not at the moment, leading to redundant manual NaN-boxing like in this case (as the argument will already be NaN-boxed). It's definitely something LLVM needs to optimise better. This doesn't affect the f16b_to_bits case as the return value is a u16, not a f16b.

Is the resolution here to create an issue in LLVM for this optimisation? Or is there something I should have done differently with the setup of the tests for RISC-V?

Created llvm/llvm-project#224119

rustbot · 2026-09-16T08:21:39Z

This PR was rebased onto a different main commit. Here's a range-diff highlighting what actually changed.

Rebasing is a normal part of keeping PRs up to date, so no action is needed—this note is just to help reviewers.

tgross35 · 2026-09-16T21:10:13Z

+// FIXME(#160859) - This should be a `#[rustc_intrinsic]` using LLVM's `fpext`
+// with this implementation constituting the fallback.
+#[inline]
+const fn widen(value: f16b) -> f32 {


Nit: this looks to be the number for the PR which means it will link to something closed. Usually FIXMEs link to open issues so we know that when they show up as closed, they can be resolved.

I'd just make it FIXME(f16b) to match our FIXME(f16)/FIXME(f128).

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tgross35 · 2026-09-16T21:11:30Z

All my concerns have been addressed but I'll leave the final review to @folkertdev. The nits commit could be squashed ofc.

rustbot added A-attributes Area: Attributes (`#[…]`, `#![…]`) A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. labels Aug 10, 2026

rustbot assigned jieyouxu Aug 10, 2026

rustbot added T-compiler Relevant to the compiler team, which will review and decide on the PR/issue. T-libs Relevant to the library team, which will review and decide on the PR/issue. labels Aug 10, 2026

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antoyo reviewed Aug 10, 2026

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Jamesbarford force-pushed the feat/fb16-pt1 branch from bf10f8a to 01c5c1b Compare August 10, 2026 14:48

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Jamesbarford force-pushed the feat/fb16-pt1 branch from 53d3660 to 40d3f6e Compare August 12, 2026 08:19

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Jamesbarford force-pushed the feat/fb16-pt1 branch from da620d0 to 0ed984f Compare August 12, 2026 10:08

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folkertdev reviewed Sep 13, 2026

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Jamesbarford force-pushed the feat/fb16-pt1 branch from a9b2c63 to 73621dc Compare September 14, 2026 11:56

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tgross35 approved these changes Sep 15, 2026

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Jamesbarford added 5 commits September 16, 2026 08:21

f16b Implementation and documentation

c21e0b3

Add F16B to Float enum & wireup trivial matches

513c294

Wire up f16b in backends

8864186

Update Tidy rules to allow for //@ revision

73747c7

Update and write tests

1b5171f

Jamesbarford force-pushed the feat/fb16-pt1 branch from 73621dc to 1b5171f Compare September 16, 2026 08:21

Address nits & add Fixme

545655d

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