perf(vpto): non-negative ranges for SIMT hardware ID ops + range-driven arith opts (floordivsi/remsi by pow2)

[jimmychou0]

Summary

Closes #1493.

Range-driven arith optimizations for SIMT scalar index math, following the
approach agreed in the issue discussion:

1. Hardware SIMT ID ops implement InferIntRangeInterface —
   get_tid_x/y/z, get_block_idx_x/y/z, get_block_dim_x/y/z,
   get_grid_dim_x/y/z, get_veccoreid, get_laneid report non-negative
   result ranges. Thread indices are tightened to [0, dim-1] when the
   enclosing pto.section.simt<<<...>>> carries static launch dims.
   Deliberately excluded (not provably non-negative): get_clock32/64
   (wraps) and get_lanemask_* (sign bit can be set).
2. New pto-arith-range-optimize pass wired into the VPTO backend
   pipeline (before VPTOSplitCVModulePass, where the SIMT queries are still
   present). It runs the upstream
   arith::createIntRangeOptimizationsPass() +
   createArithUnsignedWhenEquivalentPass() + canonicalize — no custom
   rewrite rules, so ops whose range cannot be proven are left unchanged
   (the "keep as-is when analysis fails" expectation from the issue).

With the non-negative ranges, the upstream passes rewrite
arith.floordivsi/remsi <tid>, 2^k into udiv/urem, and the LLVM backend
folds those into shifts/masks — eliminating the 9-instruction
signed-division guard chain that currently reaches every SIMT warp.

Validation

• test/lit/pto/issue1493_tid_pow2_range.pto: the issue's repro pattern
  (tid % 32 == 0 guard + (tid // 32) * 64 addressing inside
  pto.section.simt) asserts the emitted VPTO LLVM IR contains
  udiv/urem and no sdiv/srem.
• End-to-end on A5 (real device, per-token FP8 quantization kernel from the
  issue, 8192x8192):
  • unmodified .pto input now emits urem/udiv (guard chain gone);
  • final aicore .text is byte-identical to the hand-verified
    and/lshr rewrite from the issue (1112 vs 1192 bytes, −20 instruction
    words);
  • numerics pass (amax + fp8 outputs match the reference);
  • latency improves to match the hand-verified variant (0.4939 ms vs
    0.4936 ms baseline on the same box, consistent with the 0.3–0.5%
    measured on three CANN versions).
• Full ninja build of ptoas with the change on x86 CANN 9.1.0.

[jimmychou0]

Review 意见已全部修复（ad1ad0551）：

• P1 license 头：PTOArithRangeOptimize.cpp 已换成与 PTOCanonicalizeIR.cpp 相同的 PR386 OAT.3 标准头。
• P1 FileCheck 顺序：已改为 urem 在前、udiv 在后，并且用真实 FileCheck 在发射 IR 上跑过（PASS）。另注意到两个 kernel 的指令顺序不同（scf.if 内外布局差异），当前顺序按第一个 kernel 的实际布局断言。
• P2 full-range 退化：确认属实——fromUnsigned(0, 0xFFFFFFFF) 的 signed 区间因符号位翻转退化为 [INT32_MIN, INT32_MAX]，非负信息完全丢失。已把 11 个非 tid op 及 simtThreadDimUpperBound 回退值全部改为 int32 max（0x7fffffff），helper 里的死 clamp 改为 isNegative() 时 clamp 到 getSignedMaxValue，注释同步更新。lit 补了 get_block_idx_x 用例（无 section.simt dim 上界，走 [0, INT32_SIGNED_MAX] 回退路径），同样 PASS。
• P3 lit 头：已换 PR386 OAT.3。

验证：238b 全量重建 0 error；lit 两个用例（tid + block_idx）FileCheck 实跑 PASS；真实 kernel 端到端 .text 仍与手改 and/lshr 版逐字节相同（md5 6e851189，P2 修复未改变 tid 路径产出）；真机数值 AMAX+FP8 PASS，延迟 0.4919ms。

[jimmychou0]

新增：block query 的 AIC 编排路径（非 SIMT entry）现在也走 32 位 tpe intrinsic + zext，与 SIMT 路径和 CCE 前端语义一致（__builtin_cce_get_block_idx/get_block_num 是 int32_t）。此前 AIC 路径声明 i64 的 GET.BLOCK.IDX/NUM，下游 LLVM 拿不到值宽信息。两个 emitter（默认 + CANN900）同步修改，simt_block_query_vpto_llvm.pto 更新为统一形态。144 LLVM 19.1.7 全套 lit 1863 通过 / 0 失败。

[github-actions]

Warning: @jimmychou0, ci-sim exceeded its soft runtime budget.

• vpto-sim-validation runtime: 4h 4m 7s
• Soft budget: 1h 30m
• Job conclusion: failure
• Workflow run

This warning is advisory only and does not affect required checks. Please inspect the step timings for an unexpected regression.