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Pull requests: diffblue/hw-cbmc

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Pull requests list

extract verilog_set_genvarst::build_map() cleanup Verilog
#2063 opened Aug 5, 2026 by kroening Collaborator Loading…
1
KNOWNBUG test for genvar as parameter argument Tests Verilog
#2062 opened Aug 4, 2026 by kroening Collaborator Loading…
1
Verilog: narrowing a wide output port to a one-bit net Verilog
#2061 opened Aug 4, 2026 by kroening Collaborator Loading…
Print version and architecture banner
#2060 opened Aug 4, 2026 by kroening Collaborator Loading…
Verilog: accept struct/array/union as constant expressions Verilog
#2059 opened Aug 1, 2026 by kroening Collaborator Loading…
KNOWNBUG test for struct-typed parameters Tests Verilog
#2057 opened Jul 24, 2026 by kroening Collaborator Loading…
1
Verilog preprocessor: replace, not append, on macro redefinition Verilog
#2056 opened Jul 24, 2026 by kroening Collaborator Loading…
Verilog preprocessor: track bracket nesting when splitting macro arguments Verilog
#2055 opened Jul 24, 2026 by kroening Collaborator Loading…
bump CBMC dependency dependencies Pull requests that update a dependency file
#2054 opened Jul 23, 2026 by kroening Collaborator • Draft
Verilog: fold Verilog-specific constructs when propagating constants in synthesis Verilog
#2053 opened Jul 23, 2026 by kroening Collaborator • Draft
Verilog: fix three type-checker gaps from LogikBench triage Verilog
#2052 opened Jul 23, 2026 by kroening Collaborator • Draft
Verilog: grammar fixes for end labels and unpacked array parameter dimensions Verilog
#2051 opened Jul 23, 2026 by kroening Collaborator • Draft
Verilog: interpret if statements in the constant-expression interpreter Verilog
#2050 opened Jul 23, 2026 by kroening Collaborator Loading…
Verilog: don't treat 'integer' loop counters as synthesis driver conflicts Verilog
#2049 opened Jul 23, 2026 by kroening Collaborator • Draft
Verilog: fix synthesis crash on full-width part-select of signed vector Verilog
#2048 opened Jul 23, 2026 by kroening Collaborator Loading…
2
Verilog: synthesize the module instance hierarchy monolithically Verilog
#2040 opened Jul 21, 2026 by kroening Collaborator Loading…
5 tasks done
1
Verilog: typed assignment patterns Verilog
#2038 opened Jul 21, 2026 by kroening Collaborator Loading…
1
SMV word-level: support reduction and replication operators
#2037 opened Jul 21, 2026 by kroening Collaborator Loading…
1
Fix unsound fairness handling in liveness-to-safety translation engines
#2022 opened Jul 17, 2026 by kroening Collaborator • Draft
1
new IC3: recycle frame solvers after 2000 queries engines
#2020 opened Jul 16, 2026 by kroening Collaborator Loading…
2 tasks done
1
new IC3: improved obligation priority and activity decay engines
#2019 opened Jul 16, 2026 by kroening Collaborator Loading…
2 tasks done
3
new IC3: eager clause pushing in blocking and propagation engines
#2018 opened Jul 16, 2026 by kroening Collaborator Loading…
2 tasks done
1
new IC3: parent-lemma optimization and MIC_FAIL_MAX increase engines
#2017 opened Jul 16, 2026 by kroening Collaborator Loading…
2 tasks done
new IC3: polarity hinting for frame solvers engines
#2016 opened Jul 16, 2026 by kroening Collaborator Loading…
2 tasks done
new IC3: enable CTG with budget and EXCTG engines
#2015 opened Jul 16, 2026 by kroening Collaborator Loading…
2 tasks done
ProTip! What’s not been updated in a month: updated:<2026-07-06.