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Pull requests: SpinalHDL/SpinalHDL

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Pull requests list

SIM:VerilatorBackend: Fix >= 5.050 casting
#1945 opened Jul 10, 2026 by briansune Contributor Loading…
1
Use Whitelist for the dot file in the project
#1944 opened Jul 10, 2026 by inochisa Contributor Loading…
2 tasks
Refactor the TileLink peripherals with new pipeline API
#1942 opened Jun 28, 2026 by inochisa Contributor Loading…
1 of 2 tasks
LIB: MATH: fix misaligned early ready
#1941 opened Jun 26, 2026 by briansune Contributor Loading…
Add scala 2.12.21 and scala 2.13.18 version support
#1938 opened Jun 18, 2026 by inochisa Contributor Loading…
2 tasks
7
Video IPs
#1937 opened Jun 18, 2026 by briansune Contributor Loading…
41 of 42 tasks
3
Feature/okay spelling
#1927 opened Jun 2, 2026 by Tectu Contributor Loading…
1
2
fix(lib): fix premature cmd.ready assertion in UnsignedDivider
#1917 opened May 20, 2026 by Aqwyh123 Contributor Loading…
2 tasks
1
10
flatten nested concatnation operator to make RTL more friendly both for human and EDA tools
#1906 opened May 9, 2026 by facebreeze Contributor Loading…
2 tasks
4
Add default for uninitialized register in jtag
#1902 opened Apr 16, 2026 by jdavidberger Contributor Loading…
1
Add Companion trait for Bundles and MultiData types
#1898 opened Apr 7, 2026 by cyndquill Loading…
2 tasks done
1
Add support for automated Vivado IP TCL generation and simulation integration
#1859 opened Dec 19, 2025 by skylayer Contributor Loading…
3 tasks done
8
feat(sv interface): sv interface can be set to blackbox. add header comment when oneFilePerComponent
#1829 opened Oct 23, 2025 by yportne13 Contributor Loading…
2 tasks
Implement readResponseDelay in AxiMemorySim
#1820 opened Oct 1, 2025 by louiecaulfield Contributor Loading…
Add RoundType.NONE
#1798 opened Sep 9, 2025 by thajohns • Draft
2 tasks
5
Switch emit rework
#1724 opened May 5, 2025 by Dolu1990 Member Loading…
7
Change AFix division
#1722 opened May 2, 2025 by thajohns Loading…
1 of 2 tasks
4
Create IMasterSlaveDirDeclare
#1676 opened Mar 11, 2025 by g0t00 Contributor Loading…
1 of 2 tasks
4
Interface-related SystemVerilog Code Emission Enhancements
#1631 opened Dec 23, 2024 by fl4shk • Draft
2 tasks
4
Fix simulation failure with Verilator v5.x on Windows
#1618 opened Dec 10, 2024 by du33169 Loading…
2 tasks
1
7
Make 2.11 & 2.13 CI test always.
#1589 opened Nov 5, 2024 by Readon Collaborator • Draft
1 task
2
fix test initial value problem for Dfi Controller.
#1581 opened Oct 29, 2024 by Readon Collaborator Loading…
2 tasks
1
Add mill template link to readme
#1505 opened Aug 13, 2024 by mrcmry Contributor Loading…
2
Add SamplerCC pushCd(reg) -> popCd(BufferCC)
#1500 opened Aug 5, 2024 by Dolu1990 Member Loading…
set rst name for default clock domain by ClockDomainConfig
#1484 opened Jul 17, 2024 by yportne13 Contributor Loading…
3
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